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September 1997
Features
NS ESI G WD NE OR at ED F 7RH or Center ND E rt ts c 64 om / p po OM M S-65 REC See H nical Su ntersil.c i h NOT ww. Te c o ur I L o r w 8K S tact con -INTER 8 1-88
(R)
HS-6564RH
Radiation Hardened x 8, 16K x 4 CMOS RAM Module
Pinout
HS5-6564RH 40 PIN CERAMIC MODULE INTERNAL PACKAGE CODE "HSQ" TOP VIEW
*GND 1 Q4 2 D4 3 Q5 4 D5 5 A0 6 A1 7 A2 8 E3 9 *W2 10 W2 11 E4 12 A11 13 A10 14 A9 15 D6 16 Q6 17 D7 18 Q7 19 *VDD 20 40 VDD* 39 Q0 38 D0 37 Q1 36 D1 35 A6 34 A7 33 A9 32 E1 31 W1 30 W1* 29 E2 28 A3 27 A2 26 A5 25 D2 24 Q2 23 D3 22 Q3 21 GND*
* Radiation Hardened EPI CMOS - Total Dose 1 x 105 RAD (Si) - Transient Upset > 1 x 108 RAD (Si)/s - Latch-Up Free to > 1 x 1012 RAD (Si)/s * Low Power Standby 4.4mW Maximum * Low Power Operation 308mW/MHz Maximum * Data Retention 3.0V Minimum * TTL Compatible In/Out * Three State Outputs * Fast Access Time 250ns Maximum * Military Temperature Range -55oC to +125oC * On Chip Address Registers * Organizable 8K x 8 or 16K x 4 * 40 Pin DIP Pinout 2.000" x 0.900"
Description
The HS-6564RH is a radiation hardened 64K bit, synchronous CMOS RAM module. It consists of 16 HS-6504RH 4K x 1 radiation hardened CMOS RAMs, in leadless carriers, mounted on a ceramic substrate. The individual RAMs are fabricated using the Intersil radiation hardened guard ring, self-aligned silicon gate technology. The HS-6564RH is configured as an extra wide, standard length 40 pin DIP. The memory appears to the system as an array of 16 4K x 1 static RAMs. The array is organized as two 8K by 4 blocks of RAM sharing only the address bus. The data inputs, data outputs, chip enables and write enables are seperate for each block of RAM. This allows the user to organize the HS-6564RH RAM as either an 8K by 8 or a 16K by 4 array. This 64K memory provides a unique blend of low power CMOS semiconductor technology and advanced packaging techniques. The HS-6564RH is intended for use in radiation environments where a large amount of RAM is needed, and where power consumption and board space are prime concerns. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance for use in expanded memory arrays. The guaranteed low voltage data retention characteristics allow easy implementation of non-volatile readswrite memory by using very small batteries mounted directly on the memory circuit board.
A W1 E1 12
* Pins 20 and 40 (VDD) are internally connected. Similarly pins 1 and 21 (Ground) are connected. The user is advised to connect both VDD pins and both Ground pins to the board busses. This will improve power distribution across the array and will enhance decoupling. Pin 10 is internally connected to pin 11, and pin 30 is connected to pin 31. For those users wishing to preserve board compatibility with possible future RAM arrays, we recommend connections to the write lines be made at pins 11 and 31, leaving pins 10 and 30 free for future expansion.
Functional Diagram
A W EDQ
E2
D0 W2 E3
Q0
D1
Q1
D2
Q2
D3
Q3
E4
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 8-449
File Number
3032.1
Specifications HS-6564RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3.0V to +7.0V Input or Output Voltage Applied . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor . . . . . . . . . . 48mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance ja jc 40 Pin Ceramic Module Package . . . . . . TBD TBD Maximum Package Power Dissipation at +125oC 40 Pin Ceramic Module Package . . . . . . . . . . . . . . . . . . . . . .TBD Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53,336 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Standby Supply Current Operating Supply Current (8K x 8) (Note 1) Operating Supply Current (16K x 4) (Note 1) Data Retention Supply Current SYMBOL IDDSB IDDOP1 CONDITIONS IO = 0, VI = GND or VDD f = 1MHz, IO = 0 VI = VDD or GND f = 1MHz, IO = 0 VI = VDD or GND IO = 0, VDD = 3.0 VI = VDD or GND MIN MAX 1600 56 UNITS A mA
IDDOP2
-
28
mA
IDDDR
-
1200
A
Data Retention Supply Current Address Input Leakage Data Input Leakage (8K x 8) Data Input Leakage (16K x 4) Enable Input Leakage (8K x 8) Enable Input Leakage (16K x 4) Write Enable Input Leakage (Each) Output Leakage (8K x 8) Output Leakage (16K x 4) Input Low Voltage Input High Level (Except E and W) Input High Level (E and W) Output Low Voltage Output High Voltage
VDDDR IIA IID1 IID2 IIE1 IIE2 IIW IOZ1 IOZ2 VIL VIH1 GND VI VDD GND VI VDD GND VI VDD GND VI VDD GND VI VDD GND VI VDD GND VO VDD GND VO VDD
3.0 -20 -3 -5 -10 -5 -10 -20 -40 VDD -1.5
+20 +3 +5 +10 +5 +10 +20 +40 0.8 -
V A A A A A A A A V V
VIH2
VDD -1.0
-
V
VOL VOH
IOL = 2.0mA IOH = -1.0mA
2.4
0.4 -
V V
NOTES: 1. Operating supply current is proportional to operating frequency. IDDOP is specified at an operating frequency of 1MHz indicating repetitive accessing at a 1s rate. Operating at slower rates will decrease IDDOP proportionally.
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Specifications HS-6564RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Chip Enable Access Time Address Access Time (TAVQV = TELQV + TAVEL) Chip Enable Low Chip Enable High Address Setup Time Address Hold Time Write Enable Low Write Enable Setup Time Early Write Setup Time Early Write Hold Time Data Setup Time Early Write Data Setup Time Data Hold Time Early Write Data Hold Time Early Write Pulse Hold Time NOTE: 1. Inputs TRISE = TFALL 20ns: Outputs : CLOAD = 50pF. All timing measurements at 1/2 VDD. SYMBOL TELQV TAVQV Note 1 Note 1 CONDITIONS MIN MAX 350 400 UNITS ns ns
TELEH TEHEL TAVEL TELAX TWLWH TWLEH TWLEL TELWX TDVWL TDVEL TWLDX TELDX TELWH
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
350 130 50 50 150 250 10 100 10 90 100 100 250
-
ns ns ns ns ns ns ns ns ns ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Guaranteed, but not tested) LIMITS PARAMETER Address Input Capacitance Data Input Capacitance (8K x 8) Data Input Capacitance (16K x 4) Enable Input Capacitance (8K x 8) Enable Input Capacitance (16K x 4) Write Enable Input Capacitance (Each) Output Capacitance (8K x 8) Output Capacitance (16K x 4) Output Enable Time SYMBOL CIA CID1 CID2 CIE1 CIE2 CIW CONDITIONS f = 1MHz, VI = VDD or GND f = 1MHz, VI = VDD or GND f = 1MHz, VI = VDD or GND f = 1MHz, VI = VDD or GND f = 1MHz, VI = VDD or GND f = 1MHz, VI = VDD or GND MIN MAX 200 50 100 160 80 100 UNITS pF pF pF pF pF pF
CO1 CO2 TELQX
f = 1MHz, VO = VDD or GND f = 1MHz, VO = VDD or GND
-
50 100 75
pF pF ns
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Specifications HS-6564RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Guaranteed, but not tested) (Continued) LIMITS PARAMETER Output Disable Time Data Valid to Write (Read-Modify-Write) Read or Write Cycle Time NOTE: 1. Inputs: TRISE = TFALL 20ns. Outputs: CLOAD = 50pF. All timing measurements at 1/2 VDD. SYMBOL TEHQZ TQVWL CONDITIONS MIN 100 MAX 75 UNITS ns ns
TELEL
480
-
ns
TABLE 4. POST RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Output Low Voltage Output High Voltage Input Leakage Current SYMBOL VOL VOH II DELTA LIMITS 0.08V 0.48V 0.20A
NOTE: Circuits are Burned-in as HS-6504RH discrete units, see HS-6504RH for approppiate burn-in delta information.
TABLE 6. APPLICABLE SUBGROUPS NOTE: Quality Conformance Inspection (QCI) applies to the individual HS-6564RH devices, not to the assembled module. See HS-6504RH for further information.
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HS-6564RH Timing Waveforms
READ CYCLE
TELEL TAVEL TELAX A TEHEL E TELQV Q W TIME REFERENCE -1 0 1 2 3 4 5 HIGH-Z HIGH TELQX TEHQZ HIGH-Z ADD VALID TELEH TEHEL TAVEL NEXT ADD
TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 H L L INPUTS E H W X H H H H X H A X V X X X X V OUTPUT Q Z Z X V V Z Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Read Accomplished Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes
enabled but data is not valid until during time (T = 2). W must remain high until after time (T = 2). After the output data has been read, E may return high (T = 3). This will disable the output buffer and ready the RAM for the next memory cycle (T = 4).
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HS-6564RH Timing Waveforms (Continued)
EARLY WRITE CYCLE
TELAX TAVEL A ADD VALID TELEL TELEH TAVEL NEXT ADD
TEHEL E TELWH TWLEL W TELDX TDVEL D HIGH-Z Q TIME REFERENCE DATA VALID
TEHEL
TWLEL
TDVEL NEXT DATA HIGH-Z
TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 H L INPUTS E H W X L X X X L A X V X X X V D X V X X X V OUTPUT Q Z Z Z Z Z Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Write in Progress Internally Write Complete Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of E (T = 0), the addresses, the write signal, and the data input are latched in on chip registers. The logic value of W at the time E falls determines the state of the output buffer for the cycle. Since W is low when E falls, the output buffer is latched into
the high impedance state and will remain in that state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore data set up and hold times should be referenced to E. When E (T = 2) returns to the high state the output buffer disables and all signals are unlatched. The device is now ready for the next cycle.
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HS-6564RH Timing Waveforms (Continued)
READ MODIFY WRITE CYCLE
TELAX TAVEL A TEHEL E TWHEL W TQVWL TDVWL D TELQV Q HIGH-Z TELQX VALID DATA OUTPUT TWLDX DATA VALID TEHQZ HIGH-Z TWLEH TWLWH TWHEL ADD VALID TEHEL TAVEL NEXT DATA
TIME REFERENCE -1 0 1 2 3 4 5 6 7
TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 6 7 H L L L L X X X H INPUTS E H W X H H H A X V X X X X X X V D X X X X V X X X X OUTPUT Q Z Z X V V V V Z Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid, Read and Modify Time Write Begins, Data is Latched Write in Progress Internally Write Complete Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0)
The read modify write cycle begins as all other cycles on the falling edge of E (T = 0). The W line should be high at (T = 0) in order to latch the output buffers in the active state. During (T = 1) the output will be active but not valid until (T = 2). On the falling edge of the W (T = 3) the data present at the output and input are latched. The W signal also latches itself on its low going edge. All input signals excluding E have been latched and have no further effect on the RAM. The rising
edge of E (T = 5) completes the write portion of the cycle and unlatches all inputs and output. The output goes to a high impedane and the RAM is ready for the next cycle.
NOTE: In the above descriptions the numbers in parenthesis (T = n) refers to the respective timing diagrams. The numbers are located on the time reference line below each diagram. The timing diagrams shown are only examples and are not the only valid method of operation.
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HS-6564RH Organization Guide
To Organize 8K x 8: Connect: E1 with E3 E2 with E4 W1 with W2 To Organize 16K x 4: Connect: Q0 with Q4 D0 with D4 Q1 with Q5 D1 with D5 D2 with D6 Q2 with Q6 D3 with D7 Q3 with Q7 Optional W1 may be common with W2 (Pins 2 + 39) (Pins 3 + 38) (Pins 4 + 37) (Pins 5 + 36) (Pins 16 + 25) (Pins 17 + 24) (Pins 18 + 23) (Pins 19 + 22) (Pins 11 + 31) (Pins 9 + 32) (Pins 12 + 29) (Pins 11 + 31) mode, use the chip enables as if there were only two, E1 and E2. In the 16K x 4 mode, all chip enables must be treated separately. Transitions between chip enables must be treated with the same timing constraints that apply to any one chip enable. All chip enables must be high at least one chip enable high time (TEHEL) before any chip enable can fall. More than one chip enable low simultaneously, for devices whose outputs are tied common either internally or externally, is an illegal input condition and must be avoid. Printed Circuit Board Mounting: The leadless chip carrier packages used in the HS-6564RH have conductive lids. These lids are electrically floating, not connected to VDD or GND. The designer should be aware of the possibility that the carriers on the bottom side could short conductors below if pressed completely down against the surface of the circuit board. The pins on the package are designed with a standoff feature to help prevent the leadless carriers from touching the circuit board surface.
Concerns for Proper Operation of Chip Enables: The transition between blocks of RAM requires a change in the chip enable being used. When operating in the 8K x 8
HS-6504RH (One of Sixteen)
LSB A8 A7 A6 A0 A1 A2 A LATCHED ADDRESS REGISTER L 6 GATED ROW DECODER G 64 D W D Q 6 A E D L LATCH L Q LATCHED ADDRESS REGISTER 6 A ALL LINES ACTIVE HIGH-POSITIVE LOGIC THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE CONTROL AND DATA LATCHES: L LOW Q=D Q LATCHES ON RISING EDGE OF L ADDRESS LATCHES: LATCH ON RISING EDGE OF E GATED DECODERS: GATE ON RISING EDGE OF G D LATCH L LATCH L Q A G GATED COLUMN DECODER AND DATA I/O D LATCH L Q A Q 64 x 64 MATRIX
64
A 6
LSB A11 A5 A4 A3 A9 A10
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HS-6564RH Board Size Tradeoffs
Printed circuit board real estate is a costly commodity. Actual board costs depend on layout tolerances, density, complexity, number of layers, choice of board material, and other factors. The following table compares board space for 16 standard DIP 4K RAMs to the HS-6564RH RAM array. Both fine line, close tolerance layout and standard "easy" layout board sizes are shown in the comparison. We urge you to contact your local Intersil office of sales representative for accurate pricing allowing cost tradeoff analysis. In your cost analysis, also consider the advantages of a lighter, smaller overall package for your system. Con sider how much more valuable your system will be when the memory array size is decreased to about 1/6 of normal size.
64K ARRAY OR 16 4K RAMs ON A PC BOARD vs. THE HS-6564RH PACKAGE 18 Pin DIP 18 Pin DIP 18 Pin Leadless Carrier HS-6564RH CIRCUIT SUBSTRATE Standard Two Sided PCB SIZE 12 to 15 Square Inches
Fine Line or Multilayer 9 to 11 Square Inches PCB Multilayer Alumina Substrate Two Sided Mounting Multilayer Alumina Substrate 3 to 5 Square Inches 2 Square Inches
Low Voltage Data Retention
INTERSIL CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip Enable (E) must be held high during data retention; within VDD +0.3V to VDD - 0.3V. 2. All other inputs should be held either high (at CMOS VDD) or at ground to minimize IDDDR. 3. Inputs which are held high (e.g. E) must be kept between VDD +0.3V and 70% of VDD during the power up and power down transitions. 4. The RAM can begin operation one TEHEL after VDD reaches the minimum operating voltage (4.5 volts).
VDD E
DATA RETENTION MODE
DATA RETENTION MODE 4.5V VDD 3.0V 4.5V TEHEL
VDD +0.3V
Burn-In/Irradiation Circuits Intersil - Space Level Product Flow
HS4-6504RH LCCs are fully tested and processed through the Intersil space level (-Q) product flow (see page 8-91) and are assembled onto a ceramic substrate for the HS56564RH module. Temperature Cycle - 10 Cycles Serialization Electrical Tests Subgroups 1, 7, 9; Read and Record Subgroup 1 only Electrical Tests Subgroups 3, 8B, 11; Read and Record Subgroup 3 only Electrical Tests Subgroups 2, 8A, 10; Read and Record Subgroups 2 only Gross Leak Method 1014, 100% Fine Lead Method 1014, 100% Customer Source Inspection (Note 1) External Visual Inspection Method 2009 Data package Generation (Note 3)
NOTES: 1. These steps are optional, and should be listed on the purchase order if required. 2. This data comes from the testing and processing of the HS5-6504RH LCC's. 3. Data package contains: Wafer Lot Acceptance Report (includes SEM report) (Note 2) Assembly Attributes (post seal) X-Ray Report and Film (Note 2) Test Attributes (includes Group A) Test Variables Data Shippable Serial Number List Radiation Testing Certificate of Conformance (Note 2)
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